ECP5 Speed Grade -8_5G Cell Timings

Contents


DP16KD:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
CLKADOA0 135613601364 135613601364
CLKADOA1 135613601364 135613601364
CLKADOA10 135613601364 135613601364
CLKADOA11 135613601364 135613601364
CLKADOA12 135613601364 135613601364
CLKADOA13 135613601364 135613601364
CLKADOA14 135613601364 135613601364
CLKADOA15 135613601364 135613601364
CLKADOA16 135613601364 135613601364
CLKADOA17 135613601364 135613601364
CLKADOA2 135613601364 135613601364
CLKADOA3 135613601364 135613601364
CLKADOA4 135613601364 135613601364
CLKADOA5 135613601364 135613601364
CLKADOA6 135613601364 135613601364
CLKADOA7 135613601364 135613601364
CLKADOA8 135613601364 135613601364
CLKADOA9 135613601364 135613601364
CLKBDOB0 141314161419 141314161419
CLKBDOB1 141314161419 141314161419
CLKBDOB10 141314161419 141314161419
CLKBDOB11 141314161419 141314161419
CLKBDOB12 141314161419 141314161419
CLKBDOB13 141314161419 141314161419
CLKBDOB14 141314161419 141314161419
CLKBDOB15 141314161419 141314161419
CLKBDOB16 141314161419 141314161419
CLKBDOB17 141314161419 141314161419
CLKBDOB2 141314161419 141314161419
CLKBDOB3 141314161419 141314161419
CLKBDOB4 141314161419 141314161419
CLKBDOB5 141314161419 141314161419
CLKBDOB6 141314161419 141314161419
CLKBDOB7 141314161419 141314161419
CLKBDOB8 141314161419 141314161419
CLKBDOB9 141314161419 141314161419

Setup/Hold Checks

From PortTo Clock Setup (ps)Hold (ps)
MinTypMaxMinTypMax
ADA0posedge CLKA 676767 111
ADA1posedge CLKA 676767 111
ADA10posedge CLKA 676767 111
ADA11posedge CLKA 676767 111
ADA12posedge CLKA 676767 111
ADA13posedge CLKA 676767 111
ADA2posedge CLKA 676767 111
ADA3posedge CLKA 676767 111
ADA4posedge CLKA 676767 111
ADA5posedge CLKA 676767 111
ADA6posedge CLKA 676767 111
ADA7posedge CLKA 676767 111
ADA8posedge CLKA 676767 111
ADA9posedge CLKA 676767 111
ADB0posedge CLKB 575757 282828
ADB1posedge CLKB 575757 282828
ADB10posedge CLKB 575757 282828
ADB11posedge CLKB 575757 282828
ADB12posedge CLKB 575757 282828
ADB13posedge CLKB 575757 282828
ADB2posedge CLKB 575757 282828
ADB3posedge CLKB 575757 282828
ADB4posedge CLKB 575757 282828
ADB5posedge CLKB 575757 282828
ADB6posedge CLKB 575757 282828
ADB7posedge CLKB 575757 282828
ADB8posedge CLKB 575757 282828
ADB9posedge CLKB 575757 282828
CEAposedge CLKA 525252 242424
CEBposedge CLKB 858585 232323
CSA0posedge CLKA 888 515151
CSA1posedge CLKA 888 515151
CSA2posedge CLKA 888 515151
CSB0posedge CLKB 000 989898
CSB1posedge CLKB 000 989898
CSB2posedge CLKB 000 989898
DIA0posedge CLKA 595959 999
DIA1posedge CLKA 595959 999
DIA10posedge CLKA 595959 999
DIA11posedge CLKA 595959 999
DIA12posedge CLKA 595959 999
DIA13posedge CLKA 595959 999
DIA14posedge CLKA 595959 999
DIA15posedge CLKA 595959 999
DIA16posedge CLKA 595959 999
DIA17posedge CLKA 595959 999
DIA2posedge CLKA 595959 999
DIA3posedge CLKA 595959 999
DIA4posedge CLKA 595959 999
DIA5posedge CLKA 595959 999
DIA6posedge CLKA 595959 999
DIA7posedge CLKA 595959 999
DIA8posedge CLKA 595959 999
DIA9posedge CLKA 595959 999
DIB0posedge CLKB 424242 656565
DIB1posedge CLKB 424242 656565
DIB10posedge CLKB 424242 656565
DIB11posedge CLKB 424242 656565
DIB12posedge CLKB 424242 656565
DIB13posedge CLKB 424242 656565
DIB14posedge CLKB 424242 656565
DIB15posedge CLKB 424242 656565
DIB16posedge CLKB 424242 656565
DIB17posedge CLKB 424242 656565
DIB2posedge CLKB 424242 656565
DIB3posedge CLKB 424242 656565
DIB4posedge CLKB 424242 656565
DIB5posedge CLKB 424242 656565
DIB6posedge CLKB 424242 656565
DIB7posedge CLKB 424242 656565
DIB8posedge CLKB 424242 656565
DIB9posedge CLKB 424242 656565
OCEAposedge CLKA 626262 000
OCEBposedge CLKB 656565 000
RSTAposedge CLKA 147147147 000
RSTBposedge CLKB 149149149 000
WEAposedge CLKA 424242 292929
WEBposedge CLKB 000 107107107

Width Checks

Clock Width (ps)Equiv. Freq (MHz)
MinTypMaxMinTypMax
negedge CLKA 613613613 816816816
negedge CLKB 613613613 816816816
posedge CLKA 613613613 816816816
posedge CLKB 613613613 816816816

DP16KD:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
CLKADOA0 135613601364 135613601364
CLKADOA1 135613601364 135613601364
CLKADOA10 135613601364 135613601364
CLKADOA11 135613601364 135613601364
CLKADOA12 135613601364 135613601364
CLKADOA13 135613601364 135613601364
CLKADOA14 135613601364 135613601364
CLKADOA15 135613601364 135613601364
CLKADOA16 135613601364 135613601364
CLKADOA17 135613601364 135613601364
CLKADOA2 135613601364 135613601364
CLKADOA3 135613601364 135613601364
CLKADOA4 135613601364 135613601364
CLKADOA5 135613601364 135613601364
CLKADOA6 135613601364 135613601364
CLKADOA7 135613601364 135613601364
CLKADOA8 135613601364 135613601364
CLKADOA9 135613601364 135613601364
CLKBDOB0 226232239 226232239
CLKBDOB1 226232239 226232239
CLKBDOB10 226232239 226232239
CLKBDOB11 226232239 226232239
CLKBDOB12 226232239 226232239
CLKBDOB13 226232239 226232239
CLKBDOB14 226232239 226232239
CLKBDOB15 226232239 226232239
CLKBDOB16 226232239 226232239
CLKBDOB17 226232239 226232239
CLKBDOB2 226232239 226232239
CLKBDOB3 226232239 226232239
CLKBDOB4 226232239 226232239
CLKBDOB5 226232239 226232239
CLKBDOB6 226232239 226232239
CLKBDOB7 226232239 226232239
CLKBDOB8 226232239 226232239
CLKBDOB9 226232239 226232239

Setup/Hold Checks

From PortTo Clock Setup (ps)Hold (ps)
MinTypMaxMinTypMax
ADA0posedge CLKA 676767 111
ADA1posedge CLKA 676767 111
ADA10posedge CLKA 676767 111
ADA11posedge CLKA 676767 111
ADA12posedge CLKA 676767 111
ADA13posedge CLKA 676767 111
ADA2posedge CLKA 676767 111
ADA3posedge CLKA 676767 111
ADA4posedge CLKA 676767 111
ADA5posedge CLKA 676767 111
ADA6posedge CLKA 676767 111
ADA7posedge CLKA 676767 111
ADA8posedge CLKA 676767 111
ADA9posedge CLKA 676767 111
ADB0posedge CLKB 575757 282828
ADB1posedge CLKB 575757 282828
ADB10posedge CLKB 575757 282828
ADB11posedge CLKB 575757 282828
ADB12posedge CLKB 575757 282828
ADB13posedge CLKB 575757 282828
ADB2posedge CLKB 575757 282828
ADB3posedge CLKB 575757 282828
ADB4posedge CLKB 575757 282828
ADB5posedge CLKB 575757 282828
ADB6posedge CLKB 575757 282828
ADB7posedge CLKB 575757 282828
ADB8posedge CLKB 575757 282828
ADB9posedge CLKB 575757 282828
CEAposedge CLKA 525252 242424
CEBposedge CLKB 858585 232323
CSA0posedge CLKA 888 515151
CSA1posedge CLKA 888 515151
CSA2posedge CLKA 888 515151
CSB0posedge CLKB 000 989898
CSB1posedge CLKB 000 989898
CSB2posedge CLKB 000 989898
DIA0posedge CLKA 595959 999
DIA1posedge CLKA 595959 999
DIA10posedge CLKA 595959 999
DIA11posedge CLKA 595959 999
DIA12posedge CLKA 595959 999
DIA13posedge CLKA 595959 999
DIA14posedge CLKA 595959 999
DIA15posedge CLKA 595959 999
DIA16posedge CLKA 595959 999
DIA17posedge CLKA 595959 999
DIA2posedge CLKA 595959 999
DIA3posedge CLKA 595959 999
DIA4posedge CLKA 595959 999
DIA5posedge CLKA 595959 999
DIA6posedge CLKA 595959 999
DIA7posedge CLKA 595959 999
DIA8posedge CLKA 595959 999
DIA9posedge CLKA 595959 999
DIB0posedge CLKB 424242 656565
DIB1posedge CLKB 424242 656565
DIB10posedge CLKB 424242 656565
DIB11posedge CLKB 424242 656565
DIB12posedge CLKB 424242 656565
DIB13posedge CLKB 424242 656565
DIB14posedge CLKB 424242 656565
DIB15posedge CLKB 424242 656565
DIB16posedge CLKB 424242 656565
DIB17posedge CLKB 424242 656565
DIB2posedge CLKB 424242 656565
DIB3posedge CLKB 424242 656565
DIB4posedge CLKB 424242 656565
DIB5posedge CLKB 424242 656565
DIB6posedge CLKB 424242 656565
DIB7posedge CLKB 424242 656565
DIB8posedge CLKB 424242 656565
DIB9posedge CLKB 424242 656565
OCEAposedge CLKA 626262 000
OCEBposedge CLKB 656565 000
RSTAposedge CLKA 147147147 000
RSTBposedge CLKB 149149149 000
WEAposedge CLKA 424242 292929
WEBposedge CLKB 000 107107107

Width Checks

Clock Width (ps)Equiv. Freq (MHz)
MinTypMaxMinTypMax
negedge CLKA 613613613 816816816
negedge CLKB 613613613 816816816
posedge CLKA 613613613 816816816
posedge CLKB 613613613 816816816

DP16KD:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
CLKADOA0 232238245 232238245
CLKADOA1 232238245 232238245
CLKADOA10 232238245 232238245
CLKADOA11 232238245 232238245
CLKADOA12 232238245 232238245
CLKADOA13 232238245 232238245
CLKADOA14 232238245 232238245
CLKADOA15 232238245 232238245
CLKADOA16 232238245 232238245
CLKADOA17 232238245 232238245
CLKADOA2 232238245 232238245
CLKADOA3 232238245 232238245
CLKADOA4 232238245 232238245
CLKADOA5 232238245 232238245
CLKADOA6 232238245 232238245
CLKADOA7 232238245 232238245
CLKADOA8 232238245 232238245
CLKADOA9 232238245 232238245
CLKBDOB0 141314161419 141314161419
CLKBDOB1 141314161419 141314161419
CLKBDOB10 141314161419 141314161419
CLKBDOB11 141314161419 141314161419
CLKBDOB12 141314161419 141314161419
CLKBDOB13 141314161419 141314161419
CLKBDOB14 141314161419 141314161419
CLKBDOB15 141314161419 141314161419
CLKBDOB16 141314161419 141314161419
CLKBDOB17 141314161419 141314161419
CLKBDOB2 141314161419 141314161419
CLKBDOB3 141314161419 141314161419
CLKBDOB4 141314161419 141314161419
CLKBDOB5 141314161419 141314161419
CLKBDOB6 141314161419 141314161419
CLKBDOB7 141314161419 141314161419
CLKBDOB8 141314161419 141314161419
CLKBDOB9 141314161419 141314161419

Setup/Hold Checks

From PortTo Clock Setup (ps)Hold (ps)
MinTypMaxMinTypMax
ADA0posedge CLKA 676767 111
ADA1posedge CLKA 676767 111
ADA10posedge CLKA 676767 111
ADA11posedge CLKA 676767 111
ADA12posedge CLKA 676767 111
ADA13posedge CLKA 676767 111
ADA2posedge CLKA 676767 111
ADA3posedge CLKA 676767 111
ADA4posedge CLKA 676767 111
ADA5posedge CLKA 676767 111
ADA6posedge CLKA 676767 111
ADA7posedge CLKA 676767 111
ADA8posedge CLKA 676767 111
ADA9posedge CLKA 676767 111
ADB0posedge CLKB 575757 282828
ADB1posedge CLKB 575757 282828
ADB10posedge CLKB 575757 282828
ADB11posedge CLKB 575757 282828
ADB12posedge CLKB 575757 282828
ADB13posedge CLKB 575757 282828
ADB2posedge CLKB 575757 282828
ADB3posedge CLKB 575757 282828
ADB4posedge CLKB 575757 282828
ADB5posedge CLKB 575757 282828
ADB6posedge CLKB 575757 282828
ADB7posedge CLKB 575757 282828
ADB8posedge CLKB 575757 282828
ADB9posedge CLKB 575757 282828
CEAposedge CLKA 525252 242424
CEBposedge CLKB 858585 232323
CSA0posedge CLKA 888 515151
CSA1posedge CLKA 888 515151
CSA2posedge CLKA 888 515151
CSB0posedge CLKB 000 989898
CSB1posedge CLKB 000 989898
CSB2posedge CLKB 000 989898
DIA0posedge CLKA 595959 999
DIA1posedge CLKA 595959 999
DIA10posedge CLKA 595959 999
DIA11posedge CLKA 595959 999
DIA12posedge CLKA 595959 999
DIA13posedge CLKA 595959 999
DIA14posedge CLKA 595959 999
DIA15posedge CLKA 595959 999
DIA16posedge CLKA 595959 999
DIA17posedge CLKA 595959 999
DIA2posedge CLKA 595959 999
DIA3posedge CLKA 595959 999
DIA4posedge CLKA 595959 999
DIA5posedge CLKA 595959 999
DIA6posedge CLKA 595959 999
DIA7posedge CLKA 595959 999
DIA8posedge CLKA 595959 999
DIA9posedge CLKA 595959 999
DIB0posedge CLKB 424242 656565
DIB1posedge CLKB 424242 656565
DIB10posedge CLKB 424242 656565
DIB11posedge CLKB 424242 656565
DIB12posedge CLKB 424242 656565
DIB13posedge CLKB 424242 656565
DIB14posedge CLKB 424242 656565
DIB15posedge CLKB 424242 656565
DIB16posedge CLKB 424242 656565
DIB17posedge CLKB 424242 656565
DIB2posedge CLKB 424242 656565
DIB3posedge CLKB 424242 656565
DIB4posedge CLKB 424242 656565
DIB5posedge CLKB 424242 656565
DIB6posedge CLKB 424242 656565
DIB7posedge CLKB 424242 656565
DIB8posedge CLKB 424242 656565
DIB9posedge CLKB 424242 656565
OCEAposedge CLKA 626262 000
OCEBposedge CLKB 656565 000
RSTAposedge CLKA 147147147 000
RSTBposedge CLKB 149149149 000
WEAposedge CLKA 424242 292929
WEBposedge CLKB 000 107107107

Width Checks

Clock Width (ps)Equiv. Freq (MHz)
MinTypMaxMinTypMax
negedge CLKA 613613613 816816816
negedge CLKB 613613613 816816816
posedge CLKA 613613613 816816816
posedge CLKB 613613613 816816816

DP16KD:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
CLKADOA0 232238245 232238245
CLKADOA1 232238245 232238245
CLKADOA10 232238245 232238245
CLKADOA11 232238245 232238245
CLKADOA12 232238245 232238245
CLKADOA13 232238245 232238245
CLKADOA14 232238245 232238245
CLKADOA15 232238245 232238245
CLKADOA16 232238245 232238245
CLKADOA17 232238245 232238245
CLKADOA2 232238245 232238245
CLKADOA3 232238245 232238245
CLKADOA4 232238245 232238245
CLKADOA5 232238245 232238245
CLKADOA6 232238245 232238245
CLKADOA7 232238245 232238245
CLKADOA8 232238245 232238245
CLKADOA9 232238245 232238245
CLKBDOB0 226232239 226232239
CLKBDOB1 226232239 226232239
CLKBDOB10 226232239 226232239
CLKBDOB11 226232239 226232239
CLKBDOB12 226232239 226232239
CLKBDOB13 226232239 226232239
CLKBDOB14 226232239 226232239
CLKBDOB15 226232239 226232239
CLKBDOB16 226232239 226232239
CLKBDOB17 226232239 226232239
CLKBDOB2 226232239 226232239
CLKBDOB3 226232239 226232239
CLKBDOB4 226232239 226232239
CLKBDOB5 226232239 226232239
CLKBDOB6 226232239 226232239
CLKBDOB7 226232239 226232239
CLKBDOB8 226232239 226232239
CLKBDOB9 226232239 226232239

Setup/Hold Checks

From PortTo Clock Setup (ps)Hold (ps)
MinTypMaxMinTypMax
ADA0posedge CLKA 676767 111
ADA1posedge CLKA 676767 111
ADA10posedge CLKA 676767 111
ADA11posedge CLKA 676767 111
ADA12posedge CLKA 676767 111
ADA13posedge CLKA 676767 111
ADA2posedge CLKA 676767 111
ADA3posedge CLKA 676767 111
ADA4posedge CLKA 676767 111
ADA5posedge CLKA 676767 111
ADA6posedge CLKA 676767 111
ADA7posedge CLKA 676767 111
ADA8posedge CLKA 676767 111
ADA9posedge CLKA 676767 111
ADB0posedge CLKB 575757 282828
ADB1posedge CLKB 575757 282828
ADB10posedge CLKB 575757 282828
ADB11posedge CLKB 575757 282828
ADB12posedge CLKB 575757 282828
ADB13posedge CLKB 575757 282828
ADB2posedge CLKB 575757 282828
ADB3posedge CLKB 575757 282828
ADB4posedge CLKB 575757 282828
ADB5posedge CLKB 575757 282828
ADB6posedge CLKB 575757 282828
ADB7posedge CLKB 575757 282828
ADB8posedge CLKB 575757 282828
ADB9posedge CLKB 575757 282828
CEAposedge CLKA 525252 242424
CEBposedge CLKB 858585 232323
CSA0posedge CLKA 888 515151
CSA1posedge CLKA 888 515151
CSA2posedge CLKA 888 515151
CSB0posedge CLKB 000 989898
CSB1posedge CLKB 000 989898
CSB2posedge CLKB 000 989898
DIA0posedge CLKA 595959 999
DIA1posedge CLKA 595959 999
DIA10posedge CLKA 595959 999
DIA11posedge CLKA 595959 999
DIA12posedge CLKA 595959 999
DIA13posedge CLKA 595959 999
DIA14posedge CLKA 595959 999
DIA15posedge CLKA 595959 999
DIA16posedge CLKA 595959 999
DIA17posedge CLKA 595959 999
DIA2posedge CLKA 595959 999
DIA3posedge CLKA 595959 999
DIA4posedge CLKA 595959 999
DIA5posedge CLKA 595959 999
DIA6posedge CLKA 595959 999
DIA7posedge CLKA 595959 999
DIA8posedge CLKA 595959 999
DIA9posedge CLKA 595959 999
DIB0posedge CLKB 424242 656565
DIB1posedge CLKB 424242 656565
DIB10posedge CLKB 424242 656565
DIB11posedge CLKB 424242 656565
DIB12posedge CLKB 424242 656565
DIB13posedge CLKB 424242 656565
DIB14posedge CLKB 424242 656565
DIB15posedge CLKB 424242 656565
DIB16posedge CLKB 424242 656565
DIB17posedge CLKB 424242 656565
DIB2posedge CLKB 424242 656565
DIB3posedge CLKB 424242 656565
DIB4posedge CLKB 424242 656565
DIB5posedge CLKB 424242 656565
DIB6posedge CLKB 424242 656565
DIB7posedge CLKB 424242 656565
DIB8posedge CLKB 424242 656565
DIB9posedge CLKB 424242 656565
OCEAposedge CLKA 626262 000
OCEBposedge CLKB 656565 000
RSTAposedge CLKA 147147147 000
RSTBposedge CLKB 149149149 000
WEAposedge CLKA 424242 292929
WEBposedge CLKB 000 107107107

Width Checks

Clock Width (ps)Equiv. Freq (MHz)
MinTypMaxMinTypMax
negedge CLKA 613613613 816816816
negedge CLKB 613613613 816816816
posedge CLKA 613613613 816816816
posedge CLKB 613613613 816816816

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
CLKADOA0 135613601364 135613601364
CLKADOA1 135613601364 135613601364
CLKADOA10 135613601364 135613601364
CLKADOA11 135613601364 135613601364
CLKADOA12 135613601364 135613601364
CLKADOA13 135613601364 135613601364
CLKADOA14 135613601364 135613601364
CLKADOA15 135613601364 135613601364
CLKADOA16 135613601364 135613601364
CLKADOA17 135613601364 135613601364
CLKADOA2 135613601364 135613601364
CLKADOA3 135613601364 135613601364
CLKADOA4 135613601364 135613601364
CLKADOA5 135613601364 135613601364
CLKADOA6 135613601364 135613601364
CLKADOA7 135613601364 135613601364
CLKADOA8 135613601364 135613601364
CLKADOA9 135613601364 135613601364
CLKBDOB0 141314161419 141314161419
CLKBDOB1 141314161419 141314161419
CLKBDOB10 141314161419 141314161419
CLKBDOB11 141314161419 141314161419
CLKBDOB12 141314161419 141314161419
CLKBDOB13 141314161419 141314161419
CLKBDOB14 141314161419 141314161419
CLKBDOB15 141314161419 141314161419
CLKBDOB16 141314161419 141314161419
CLKBDOB17 141314161419 141314161419
CLKBDOB2 141314161419 141314161419
CLKBDOB3 141314161419 141314161419
CLKBDOB4 141314161419 141314161419
CLKBDOB5 141314161419 141314161419
CLKBDOB6 141314161419 141314161419
CLKBDOB7 141314161419 141314161419
CLKBDOB8 141314161419 141314161419
CLKBDOB9 141314161419 141314161419

Setup/Hold Checks

From PortTo Clock Setup (ps)Hold (ps)
MinTypMaxMinTypMax
ADA0posedge CLKA 676767 111
ADA1posedge CLKA 676767 111
ADA10posedge CLKA 676767 111
ADA11posedge CLKA 676767 111
ADA12posedge CLKA 676767 111
ADA13posedge CLKA 676767 111
ADA2posedge CLKA 676767 111
ADA3posedge CLKA 676767 111
ADA4posedge CLKA 676767 111
ADA5posedge CLKA 676767 111
ADA6posedge CLKA 676767 111
ADA7posedge CLKA 676767 111
ADA8posedge CLKA 676767 111
ADA9posedge CLKA 676767 111
ADB0posedge CLKB 575757 282828
ADB1posedge CLKB 575757 282828
ADB10posedge CLKB 575757 282828
ADB11posedge CLKB 575757 282828
ADB12posedge CLKB 575757 282828
ADB13posedge CLKB 575757 282828
ADB2posedge CLKB 575757 282828
ADB3posedge CLKB 575757 282828
ADB4posedge CLKB 575757 282828
ADB5posedge CLKB 575757 282828
ADB6posedge CLKB 575757 282828
ADB7posedge CLKB 575757 282828
ADB8posedge CLKB 575757 282828
ADB9posedge CLKB 575757 282828
CEAposedge CLKA 525252 242424
CEBposedge CLKB 858585 232323
CSA0posedge CLKA 888 515151
CSA1posedge CLKA 888 515151
CSA2posedge CLKA 888 515151
CSB0posedge CLKB 000 989898
CSB1posedge CLKB 000 989898
CSB2posedge CLKB 000 989898
DIA0posedge CLKA 595959 999
DIA1posedge CLKA 595959 999
DIA10posedge CLKA 595959 999
DIA11posedge CLKA 595959 999
DIA12posedge CLKA 595959 999
DIA13posedge CLKA 595959 999
DIA14posedge CLKA 595959 999
DIA15posedge CLKA 595959 999
DIA16posedge CLKA 595959 999
DIA17posedge CLKA 595959 999
DIA2posedge CLKA 595959 999
DIA3posedge CLKA 595959 999
DIA4posedge CLKA 595959 999
DIA5posedge CLKA 595959 999
DIA6posedge CLKA 595959 999
DIA7posedge CLKA 595959 999
DIA8posedge CLKA 595959 999
DIA9posedge CLKA 595959 999
DIB0posedge CLKB 424242 656565
DIB1posedge CLKB 424242 656565
DIB10posedge CLKB 424242 656565
DIB11posedge CLKB 424242 656565
DIB12posedge CLKB 424242 656565
DIB13posedge CLKB 424242 656565
DIB14posedge CLKB 424242 656565
DIB15posedge CLKB 424242 656565
DIB16posedge CLKB 424242 656565
DIB17posedge CLKB 424242 656565
DIB2posedge CLKB 424242 656565
DIB3posedge CLKB 424242 656565
DIB4posedge CLKB 424242 656565
DIB5posedge CLKB 424242 656565
DIB6posedge CLKB 424242 656565
DIB7posedge CLKB 424242 656565
DIB8posedge CLKB 424242 656565
DIB9posedge CLKB 424242 656565
OCEAposedge CLKA 626262 000
OCEBposedge CLKB 656565 000
RSTAposedge CLKA 147147147 000
RSTBposedge CLKB 149149149 000
WEAposedge CLKA 424242 292929
WEBposedge CLKB 000 107107107

Width Checks

Clock Width (ps)Equiv. Freq (MHz)
MinTypMaxMinTypMax
negedge CLKA 613613613 816816816
negedge CLKB 613613613 816816816
posedge CLKA 613613613 816816816
posedge CLKB 613613613 816816816

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
CLKADOA0 135613601364 135613601364
CLKADOA1 135613601364 135613601364
CLKADOA10 135613601364 135613601364
CLKADOA11 135613601364 135613601364
CLKADOA12 135613601364 135613601364
CLKADOA13 135613601364 135613601364
CLKADOA14 135613601364 135613601364
CLKADOA15 135613601364 135613601364
CLKADOA16 135613601364 135613601364
CLKADOA17 135613601364 135613601364
CLKADOA2 135613601364 135613601364
CLKADOA3 135613601364 135613601364
CLKADOA4 135613601364 135613601364
CLKADOA5 135613601364 135613601364
CLKADOA6 135613601364 135613601364
CLKADOA7 135613601364 135613601364
CLKADOA8 135613601364 135613601364
CLKADOA9 135613601364 135613601364
CLKBDOB0 141414171420 141414171420
CLKBDOB1 141414171420 141414171420
CLKBDOB10 141414171420 141414171420
CLKBDOB11 141414171420 141414171420
CLKBDOB12 141414171420 141414171420
CLKBDOB13 141414171420 141414171420
CLKBDOB14 141414171420 141414171420
CLKBDOB15 141414171420 141414171420
CLKBDOB16 141414171420 141414171420
CLKBDOB17 141414171420 141414171420
CLKBDOB2 141414171420 141414171420
CLKBDOB3 141414171420 141414171420
CLKBDOB4 141414171420 141414171420
CLKBDOB5 141414171420 141414171420
CLKBDOB6 141414171420 141414171420
CLKBDOB7 141414171420 141414171420
CLKBDOB8 141414171420 141414171420
CLKBDOB9 141414171420 141414171420

Setup/Hold Checks

From PortTo Clock Setup (ps)Hold (ps)
MinTypMaxMinTypMax
ADA0posedge CLKA 676767 111
ADA1posedge CLKA 676767 111
ADA10posedge CLKA 676767 111
ADA11posedge CLKA 676767 111
ADA12posedge CLKA 676767 111
ADA13posedge CLKA 676767 111
ADA2posedge CLKA 676767 111
ADA3posedge CLKA 676767 111
ADA4posedge CLKA 676767 111
ADA5posedge CLKA 676767 111
ADA6posedge CLKA 676767 111
ADA7posedge CLKA 676767 111
ADA8posedge CLKA 676767 111
ADA9posedge CLKA 676767 111
ADB0posedge CLKB 575757 282828
ADB1posedge CLKB 575757 282828
ADB10posedge CLKB 575757 282828
ADB11posedge CLKB 575757 282828
ADB12posedge CLKB 575757 282828
ADB13posedge CLKB 575757 282828
ADB2posedge CLKB 575757 282828
ADB3posedge CLKB 575757 282828
ADB4posedge CLKB 575757 282828
ADB5posedge CLKB 575757 282828
ADB6posedge CLKB 575757 282828
ADB7posedge CLKB 575757 282828
ADB8posedge CLKB 575757 282828
ADB9posedge CLKB 575757 282828
CEAposedge CLKA 525252 242424
CEBposedge CLKB 858585 232323
CSA0posedge CLKA 888 515151
CSA1posedge CLKA 888 515151
CSA2posedge CLKA 888 515151
CSB0posedge CLKB 000 989898
CSB1posedge CLKB 000 989898
CSB2posedge CLKB 000 989898
DIA0posedge CLKA 595959 999
DIA1posedge CLKA 595959 999
DIA10posedge CLKA 595959 999
DIA11posedge CLKA 595959 999
DIA12posedge CLKA 595959 999
DIA13posedge CLKA 595959 999
DIA14posedge CLKA 595959 999
DIA15posedge CLKA 595959 999
DIA16posedge CLKA 595959 999
DIA17posedge CLKA 595959 999
DIA2posedge CLKA 595959 999
DIA3posedge CLKA 595959 999
DIA4posedge CLKA 595959 999
DIA5posedge CLKA 595959 999
DIA6posedge CLKA 595959 999
DIA7posedge CLKA 595959 999
DIA8posedge CLKA 595959 999
DIA9posedge CLKA 595959 999
DIB0posedge CLKB 424242 656565
DIB1posedge CLKB 424242 656565
DIB10posedge CLKB 424242 656565
DIB11posedge CLKB 424242 656565
DIB12posedge CLKB 424242 656565
DIB13posedge CLKB 424242 656565
DIB14posedge CLKB 424242 656565
DIB15posedge CLKB 424242 656565
DIB16posedge CLKB 424242 656565
DIB17posedge CLKB 424242 656565
DIB2posedge CLKB 424242 656565
DIB3posedge CLKB 424242 656565
DIB4posedge CLKB 424242 656565
DIB5posedge CLKB 424242 656565
DIB6posedge CLKB 424242 656565
DIB7posedge CLKB 424242 656565
DIB8posedge CLKB 424242 656565
DIB9posedge CLKB 424242 656565
OCEAposedge CLKA 626262 000
OCEBposedge CLKB 656565 000
RSTAposedge CLKA 147147147 000
RSTBposedge CLKB 149149149 000
WEAposedge CLKA 424242 292929
WEBposedge CLKB 000 107107107

Width Checks

Clock Width (ps)Equiv. Freq (MHz)
MinTypMaxMinTypMax
negedge CLKA 613613613 816816816
negedge CLKB 777777777 644644644
posedge CLKA 613613613 816816816
posedge CLKB 777777777 644644644

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
CLKADOA0 135613601364 135613601364
CLKADOA1 135613601364 135613601364
CLKADOA10 135613601364 135613601364
CLKADOA11 135613601364 135613601364
CLKADOA12 135613601364 135613601364
CLKADOA13 135613601364 135613601364
CLKADOA14 135613601364 135613601364
CLKADOA15 135613601364 135613601364
CLKADOA16 135613601364 135613601364
CLKADOA17 135613601364 135613601364
CLKADOA2 135613601364 135613601364
CLKADOA3 135613601364 135613601364
CLKADOA4 135613601364 135613601364
CLKADOA5 135613601364 135613601364
CLKADOA6 135613601364 135613601364
CLKADOA7 135613601364 135613601364
CLKADOA8 135613601364 135613601364
CLKADOA9 135613601364 135613601364
CLKBDOB0 141414171420 141414171420
CLKBDOB1 141414171420 141414171420
CLKBDOB10 141414171420 141414171420
CLKBDOB11 141414171420 141414171420
CLKBDOB12 141414171420 141414171420
CLKBDOB13 141414171420 141414171420
CLKBDOB14 141414171420 141414171420
CLKBDOB15 141414171420 141414171420
CLKBDOB16 141414171420 141414171420
CLKBDOB17 141414171420 141414171420
CLKBDOB2 141414171420 141414171420
CLKBDOB3 141414171420 141414171420
CLKBDOB4 141414171420 141414171420
CLKBDOB5 141414171420 141414171420
CLKBDOB6 141414171420 141414171420
CLKBDOB7 141414171420 141414171420
CLKBDOB8 141414171420 141414171420
CLKBDOB9 141414171420 141414171420

Setup/Hold Checks

From PortTo Clock Setup (ps)Hold (ps)
MinTypMaxMinTypMax
ADA0posedge CLKA 676767 111
ADA1posedge CLKA 676767 111
ADA10posedge CLKA 676767 111
ADA11posedge CLKA 676767 111
ADA12posedge CLKA 676767 111
ADA13posedge CLKA 676767 111
ADA2posedge CLKA 676767 111
ADA3posedge CLKA 676767 111
ADA4posedge CLKA 676767 111
ADA5posedge CLKA 676767 111
ADA6posedge CLKA 676767 111
ADA7posedge CLKA 676767 111
ADA8posedge CLKA 676767 111
ADA9posedge CLKA 676767 111
ADB0posedge CLKB 575757 282828
ADB1posedge CLKB 575757 282828
ADB10posedge CLKB 575757 282828
ADB11posedge CLKB 575757 282828
ADB12posedge CLKB 575757 282828
ADB13posedge CLKB 575757 282828
ADB2posedge CLKB 575757 282828
ADB3posedge CLKB 575757 282828
ADB4posedge CLKB 575757 282828
ADB5posedge CLKB 575757 282828
ADB6posedge CLKB 575757 282828
ADB7posedge CLKB 575757 282828
ADB8posedge CLKB 575757 282828
ADB9posedge CLKB 575757 282828
CEAposedge CLKA 525252 242424
CEBposedge CLKB 858585 232323
CSA0posedge CLKA 888 515151
CSA1posedge CLKA 888 515151
CSA2posedge CLKA 888 515151
CSB0posedge CLKB 000 989898
CSB1posedge CLKB 000 989898
CSB2posedge CLKB 000 989898
DIA0posedge CLKA 595959 999
DIA1posedge CLKA 595959 999
DIA10posedge CLKA 595959 999
DIA11posedge CLKA 595959 999
DIA12posedge CLKA 595959 999
DIA13posedge CLKA 595959 999
DIA14posedge CLKA 595959 999
DIA15posedge CLKA 595959 999
DIA16posedge CLKA 595959 999
DIA17posedge CLKA 595959 999
DIA2posedge CLKA 595959 999
DIA3posedge CLKA 595959 999
DIA4posedge CLKA 595959 999
DIA5posedge CLKA 595959 999
DIA6posedge CLKA 595959 999
DIA7posedge CLKA 595959 999
DIA8posedge CLKA 595959 999
DIA9posedge CLKA 595959 999
DIB0posedge CLKB 424242 656565
DIB1posedge CLKB 424242 656565
DIB10posedge CLKB 424242 656565
DIB11posedge CLKB 424242 656565
DIB12posedge CLKB 424242 656565
DIB13posedge CLKB 424242 656565
DIB14posedge CLKB 424242 656565
DIB15posedge CLKB 424242 656565
DIB16posedge CLKB 424242 656565
DIB17posedge CLKB 424242 656565
DIB2posedge CLKB 424242 656565
DIB3posedge CLKB 424242 656565
DIB4posedge CLKB 424242 656565
DIB5posedge CLKB 424242 656565
DIB6posedge CLKB 424242 656565
DIB7posedge CLKB 424242 656565
DIB8posedge CLKB 424242 656565
DIB9posedge CLKB 424242 656565
OCEAposedge CLKA 626262 000
OCEBposedge CLKB 656565 000
RSTAposedge CLKA 147147147 000
RSTBposedge CLKB 149149149 000
WEAposedge CLKA 424242 292929
WEBposedge CLKB 000 107107107

Width Checks

Clock Width (ps)Equiv. Freq (MHz)
MinTypMaxMinTypMax
negedge CLKA 613613613 816816816
negedge CLKB 609609609 821821821
posedge CLKA 613613613 816816816
posedge CLKB 609609609 821821821

PIO:IOTYPE=LVCMOS12

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
PADPADDI 594610626 594610626
PADDOPAD 134715131679 134715131679
PADDTPAD 155418002047 155418002047

Width Checks

Clock Width (ps)Equiv. Freq (MHz)
MinTypMaxMinTypMax
negedge PAD 250025002500 200200200
posedge PAD 250025002500 200200200

PIO:IOTYPE=LVCMOS15

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
PADPADDI 146414741484 146414741484
PADDOPAD 139615531711 139615531711
PADDTPAD 155317341915 155317341915

Width Checks

Clock Width (ps)Equiv. Freq (MHz)
MinTypMaxMinTypMax
negedge PAD 250025002500 200200200
posedge PAD 250025002500 200200200

PIO:IOTYPE=LVCMOS18

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
PADPADDI 114511911237 114511911237
PADDOPAD 144115871734 144115871734
PADDTPAD 175018882027 175018882027

Width Checks

Clock Width (ps)Equiv. Freq (MHz)
MinTypMaxMinTypMax
negedge PAD 250025002500 200200200
posedge PAD 250025002500 200200200

PIO:IOTYPE=LVCMOS25

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
PADPADDI 826851876 826851876
PADDOPAD 173617511766 173617511766
PADDTPAD 174718431940 174718431940

Width Checks

Clock Width (ps)Equiv. Freq (MHz)
MinTypMaxMinTypMax
negedge PAD 250025002500 200200200
posedge PAD 250025002500 200200200

PIO:IOTYPE=LVCMOS33

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
PADPADDI 921945970 921945970
PADDOPAD 181920062193 181920062193
PADDTPAD 211323272542 211323272542

Width Checks

Clock Width (ps)Equiv. Freq (MHz)
MinTypMaxMinTypMax
negedge PAD 250025002500 200200200
posedge PAD 250025002500 200200200

PIO:IOTYPE=LVDS

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
PADPADDI 437437437 437437437
PADDOPAD 957958959 957958959

Width Checks

Clock Width (ps)Equiv. Freq (MHz)
MinTypMaxMinTypMax
negedge PAD 125012501250 400400400
posedge PAD 125012501250 400400400

PIO:IOTYPE=SSTL15_I

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
PADPADDI 403413424 403413424
PADDOPAD 175818621966 175818621966
PADDTPAD 182124193017 182124193017

Width Checks

Clock Width (ps)Equiv. Freq (MHz)
MinTypMaxMinTypMax
negedge PAD 125012501250 400400400
posedge PAD 125012501250 400400400

PIO:IOTYPE=SSTL15_II

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
PADPADDI 403413424 403413424
PADDOPAD 167817521827 167817521827
PADDTPAD 166124323203 166124323203

Width Checks

Clock Width (ps)Equiv. Freq (MHz)
MinTypMaxMinTypMax
negedge PAD 125012501250 400400400
posedge PAD 125012501250 400400400

PIO:IOTYPE=SSTL18_I

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
PADPADDI 399411423 399411423
PADDOPAD 181819132008 181819132008
PADDTPAD 195423792805 195423792805

Width Checks

Clock Width (ps)Equiv. Freq (MHz)
MinTypMaxMinTypMax
negedge PAD 125012501250 400400400
posedge PAD 125012501250 400400400

PIO:IOTYPE=SSTL18_II

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
PADPADDI 399411423 399411423
PADDOPAD 158416481712 158416481712
PADDTPAD 151924313344 151924313344

Width Checks

Clock Width (ps)Equiv. Freq (MHz)
MinTypMaxMinTypMax
negedge PAD 125012501250 400400400
posedge PAD 125012501250 400400400

SCCU2C

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
A0F0 119130141 119130141
A0F1 352372392 352372392
A0FCO 112195278 112195278
A1F1 119130141 119130141
A1FCO 112195278 112195278
B0F0 119130141 119130141
B0F1 352372392 352372392
B0FCO 112195278 112195278
B1F1 119130141 119130141
B1FCO 112195278 112195278
C0F0 119130141 119130141
C0F1 352372392 352372392
C0FCO 112195278 112195278
C1F1 119130141 119130141
C1FCO 112195278 112195278
CLKQ0 257283309 257283309
CLKQ1 257282308 257282308
D0F0 119130141 119130141
D0F1 352372392 352372392
D0FCO 112195278 112195278
D1F1 119130141 119130141
D1FCO 112195278 112195278
FCIF0 140198257 140198257
FCIF1 201237273 201237273
FCIFCO 394143 394143

Setup/Hold Checks

From PortTo Clock Setup (ps)Hold (ps)
MinTypMaxMinTypMax
CEposedge CLK 000 888990
DI0posedge CLK 000 166173181
DI0posedge CLK 000 167174181
DI1posedge CLK 000 166173181
LSRposedge CLK 146185224 000
LSRposedge CLK 146185225 000

Width Checks

Clock Width (ps)Equiv. Freq (MHz)
MinTypMaxMinTypMax
negedge CLK 889889889 562562562
negedge LSR 444444444 112611261126
posedge CLK 889889889 562562562
posedge LSR 444444444 112611261126

SDPRAME

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
CLKQ0 257283309 257283309
CLKQ1 257282308 257282308
RAD0F0 119130141 119130141
RAD0F1 119130141 119130141
RAD1F0 119130141 119130141
RAD1F1 119130141 119130141
RAD2F0 119130141 119130141
RAD2F1 119130141 119130141
RAD3F0 119130141 119130141
RAD3F1 119130141 119130141
WCKF0 553556559 553556559
WCKF1 555558562 555558562

Setup/Hold Checks

From PortTo Clock Setup (ps)Hold (ps)
MinTypMaxMinTypMax
DI0posedge CLK 000 166173181
DI1posedge CLK 000 166173181
WAD0posedge WCK 000 175194213
WAD1posedge WCK 000 181199217
WAD2posedge WCK 000 169189209
WAD3posedge WCK 000 179197215
WD0posedge WCK 000 132153175
WD1posedge WCK 000 134154174
WREposedge WCK 143175208 000

Width Checks

Clock Width (ps)Equiv. Freq (MHz)
MinTypMaxMinTypMax
negedge CLK 889889889 562562562
negedge WCK 444444444 112611261126
posedge CLK 889889889 562562562
posedge WCK 444444444 112611261126

SLOGICB

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
A0F0 119130141 119130141
A0OFX0 156197239 156197239
A1F1 119130141 119130141
A1OFX0 156197239 156197239
B0F0 119130141 119130141
B0OFX0 156197239 156197239
B1F1 119130141 119130141
B1OFX0 156197239 156197239
C0F0 119130141 119130141
C0OFX0 156197239 156197239
C1F1 119130141 119130141
C1OFX0 156197239 156197239
CLKQ0 257283309 257283309
CLKQ1 257282308 257282308
D0F0 119130141 119130141
D0OFX0 156197239 156197239
D1F1 119130141 119130141
D1OFX0 156197239 156197239
FXAOFX1 111125140 111125140
FXBOFX1 111126141 111126141
M0OFX0 113132151 113132151
M1OFX1 113130148 113130148

Setup/Hold Checks

From PortTo Clock Setup (ps)Hold (ps)
MinTypMaxMinTypMax
CEposedge CLK 000 888990
DI0posedge CLK 000 166173181
DI0posedge CLK 000 167174181
DI1posedge CLK 000 166173181
LSRposedge CLK 146185225 000
M0posedge CLK 000 153167181
M1posedge CLK 000 153167181

Width Checks

Clock Width (ps)Equiv. Freq (MHz)
MinTypMaxMinTypMax
negedge CLK 889889889 562562562
negedge LSR 444444444 112611261126
posedge CLK 889889889 562562562
posedge LSR 444444444 112611261126

SRAMWB

Propagation Delays

From PortTo Port Low-High Transition (ps)High-Low Transition (ps)
MinTypMaxMinTypMax
A0WADO3 000 000
A1WDO1 000 000
B0WADO1 000 000
B1WDO3 000 000
C0WADO2 000 000
C1WDO0 000 000
D0WADO0 000 000
D1WDO2 000 000