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The SymbiFlow toolchain consists of logic synthesis and implementation tools, as well as chip documentation projects for chips of various vendors. To prepare a working bitstream for a particular FPGA chip, the toolchain goes through the following stages.
First, a description of the FPGA chip is created with the information from the relevant bitstream documentation project. This part is done within the SymbiFlow Architecture Definitions. The project prepares information about the timings and resources available in the chip needed at the implementation stage, as well as techmaps for the synthesis tools.
The second step is logic synthesis. It is carried out in the Yosys framework, which expresses the input Verilog file by means of the block and connection types available in the chosen chip.
The next step is implementation. Placement and routing tools put individual blocks from the synthesis description in the specific chip locations and create paths between them. To do that, SymbiFlow uses either nextpnr or Verilog to Routing.
Finally, the design properties are translated into a set of features available in the given FPGA chip. These features are saved in the fasm format, which is developed as part of SymbiFlow. The fasm file is then translated to bitstream using the information from the bitstream documentation projects.
Project X-Ray aims to provide information to develop a free and open Verilog to bitstream toolchain for the Xilinx 7-Series FPGA architecture.learn more
Project Trellis enables a fully open-source flow for ECP5 FPGAs using Yosys for Verilog synthesis and nextpnr for place and route, providing the device database and tools for bitstream creation.learn more
Project IceStorm was the first bitstream documentation project that started the idea of a fully Open-Source flow for FPGA chips. It documents the whole iCE40 chip.learn more