SymbiFlow will be a FOSS Verilog-to-Bitstream FPGA synthesis flow for Xilinx 7-Series FPGAs and iCE40. It is under construction. This page describes briefly what we are up to.
Project X-Ray aims at documenting the Xilinx 7-series bit-stream format, a prerequisite to building Open Source tools to generate bit-streams for those devices. The information currently on this page is a sneak preview for the kind of information Project X-Ray will provide.
Currently the work focuses on the Artix-7 xc7a50tfgg484-1 device. But we hope to be able to provide documentation for all Xilinx 7-Series, UltraScale, and UltraScale+ devices in the long term.
Right now we focus on the region SLICE_X12Y100:SLICE_X27Y149 on the xc7a50tfgg484-1 device (configuration frames 0x00020500:0x000208ff). The immediate goal of the project is to provide tools to create bit-streams for partial reconfiguration of this region only.
The documentation is available in two formats:
We will update the information on this page and provide more documentation on the format we use to document the bit-stream in the near future.
Check out our github page if you want to peek at our methodology. The short description is this: We run many small designs through Vivado and use the TCL API to constrain the designs so that they have certain properties, then read the generated bit-streams and run a simple statistical analysis to correlate the bit-stream bits with features in the test designs.
Project X-Ray also includes command line tools for reading/writing Xilinx bit-stream files and converting them to/from simpler-to-process text-based formats.
Project IceStorm is a previous project that documented the iCE40 bit-stream format. It will become a part of SymbiFlow. SymbiFlow will support the old Yosys-ArachnePnr-IceStorm flow but will also add a Yosys-VPR-IceStorm flow.