SymbiFlow aims at building FPGA tooling that is:
SymbiFlow is meant to enable new innovation, as well as optimisation and automation of FPGA development workflows, to help make FPGA more accessible to a broad community of software developers who might otherwise be discouraged by the closed and vendor-specific workflows of today.
To understand how SymbiFlow works, it is best to start with an overview of the general EDA tooling ecosystem and then proceed to see what parts constitute the SymbiFlow project.
For both ASIC- and FPGA-oriented EDA tooling, there are three major areas that the workflow needs to cover: hardware description, frontend and backend.
Hardware description languages are generally open, with both established HDLs such as Verilog and VHDL and emerging software-inspired paradigms like Chisel, SpinalHDL or MiGen. The major problem lies however in the front- and backend, where previously there was no established standard, vendor-neutral tooling that would cover all the necessary components for an end-to-end flow.
This pertains both to ASIC and FPGA workflows, although SymbiFlow focuses on the latter (some parts of SymbiFlow will also be useful in the former).
To achieve SymbiFlow's goal of a complete FOSS FPGA toolchain, a number of tools and projects are necessary to provide all the needed components of an end-to-end flow. Thus, SymbiFlow serves as an umbrella project for several activities, the central of which pertains to the creation of so-called FPGA "architecture definitions", i.e. documentation of how specific FPGAs work internally.
Those definitions and serve as input to backend tools like nextpnr and Verilog to Routing, and frontend tools like Yosys. They are created within separate collaborating projects targeting different FPGAs - Project X-Ray for Xilinx 7-Series, Project IceStorm for Lattice iCE40 and Project Trellis for Lattice ECP5 FPGAs.
|Project IceStorm||Project X‑Ray||Project Trellis||Project 2064|
Project X-Ray aims at documenting the Xilinx 7-series bit-stream format, a prerequisite to building Open Source tools to generate bit-streams for those devices.learn more
Project Trellis aims at documenting the Lattice ECP5 bit-stream, so that Open Source tools can be built.learn more
Project IceStorm is a previous project that documented the iCE40 bit-stream format. It will become a part of SymbiFlow.learn more
Project X-Ray aims at documenting the Xilinx 7-series bit-stream format, a prerequisite to building Open Source tools to generate bit-streams for those devices. The information currently on this page is a sneak preview for the kind of information Project X-Ray will provide.
Currently the work focuses on the Artix-7 xc7a50tfgg484-1 device. But we hope to be able to provide documentation for all Xilinx 7-Series, UltraScale, and UltraScale+ devices in the long term.
Right now we focus on the region SLICE_X12Y100:SLICE_X27Y149 on the xc7a50tfgg484-1 device (configuration frames 0x00020500:0x000208ff). The immediate goal of the project is to provide tools to create bit-streams for partial reconfiguration of this region only.
We will update the information on this page and provide more documentation on the format we use to document the bit-stream in the near future.
Check out our github page if you want to peek at our methodology. The short description is this: We run many small designs through Vivado and use the TCL API to constrain the designs so that they have certain properties, then read the generated bit-streams and run a simple statistical analysis to correlate the bit-stream bits with features in the test designs.
More documentation can be found published on prjxray ReadTheDocs site - this includes:
Project X-Ray also includes command line tools for reading / writing Xilinx bit-stream files and converting them to / from simpler-to-process text-based formats.
Project Trellis aims at documenting the Lattice ECP5 bit-stream, so that Open Source tools can be built. Project Trellis is used to build the ECP5 device database for nextpnr and generate bitstreams for designs placed and routed with nextpnr. Project Trellis contains bitstream documentation for almost all functionality of the ECP5 - including logic, BRAM, multipliers, IO, PLLs, and SERDES. Project Trellis also includes timing data for logic, BRAM and basic interconnect.
The vast majority of Project Trellis applies to all ECP5 parts and may also apply to related Lattice parts such as the CrossLink FPGAs. IO and global network data is included for all ECP5 parts, and timing data is included for all speed grades.
Project IceStorm is a previous project that documented the iCE40 bit-stream format. It will become a part of SymbiFlow. SymbiFlow will support the old Yosys-ArachnePnr-IceStorm flow but will also add a Yosys-VPR-IceStorm flow.
SymbiFlow is a collaborative project and we welcome your contributions. The code is available on GitHub, and HTML documentation is available on Read The Docs.
Are you interested in helping this project move forward? There are multiple areas and technologies we need help with - reach out to us, we’re sure we will find something for you.